MIL-STD-1553 A, B & McAir
PCI BUS Interface Card
* SUPPORTS VALIDATION/PRODUCTION TEST PLANS.
* SIMULTANEOUS BC, MULTIPLE RTS, MONITOR.
* 1553A. B, McAir AND USER DEFINED PROTOCOLS.
* 16/32 BIT TIME TAG.
* FULL ERROR DETECTION AND GENERATION.
* ON BOARD MAJOR/MINOR FRAME TIMING.
* PROGRAMMABLE MESSAGE PARAMETERS.
* PROGRAMMABLE OUTPUT AMPLITUDE.
* SOFTWARE WITH SOURCE CODE INCLUDED.
* AUTO INCREMENTING MEMORY STORAGE
* 128K x 16 DUAL PORT STATIC RAM.
† Size†††† PCI 1/2 size
† Type†††† 32 Bits, 3.3 / 5 Volts, Target only.
†††† The PCI301 is a full-featured, high performance, Dual Redundant MIL-STD-1553 serial bus Simulator Analyzer Tester designed as a plug in card for a PCI backplane. The PCI301 includes full error injection and can operate in indepen≠dent or simultaneous mode as a Bus Controller, multiple simulated Remote Terminals and full/sele≠ctive Monitor. Its data structure can be changed on the fly without interrupting the processor for real time operation. The active monitor stores, time tag and annotates bus traffic with the message type and any detected errors. Stored words are annotated with a break down of the word error.
†††† The PCI301 can be used for Validation Testing, Production Testing, full bus simulation and monitoring, as a general purpose 1553 interface or a stand alone bus Analyzer. For precise message scheduling and measurements, the Major and minor frame times are independent of message sequences or retransmissions on errors and the start of all command messages are independent of message length, response time or length of response. Message timing is calibrated and RT responses have low jitter.
†† G E N E R A L
S P E C I F I C A T I O N S
Major Frame Count
Major Frame Size
Min≠or Frame Time
Minor Frame Size
Response Timeout Response Time
Retry on Error
Internal time tag
128K x 16
1 to 32768, Continuous†††††††††
1 to 1024 Minor Frames
0 to 32766 Commands††††††††††††
0 to 2048
2 to 6400 usec. in .1 sec. steps
2 to 33 usec. in .5 usec. steps†††† 2 to 33 usec. in .5 usec. steps††
50ns Max† †††††††††††††††††††††††
Same or alternate bus††††††††††††
1, 6.4 or 64 usec. steps†††
‑ Low bit count††† (1, 2)†††††††††††††††††††††††
‑ High bit count†† (1, 2, 3)††††††††††††††††††††
‑ Parity error††† ††††††††††††††††††††††††††††††††††††††††††
‑ Manchester low†††††††††††††††††††††††††††††††††††††††††††
‑ Manchester high††††††††††††††††††††††††††††††††††††††††††
‑ Inverted Sync††††††††††††††††††††††††††††††††††††††††††††
‑ Zero crossing deviation (+/- 150 nsec, External)
- Response/Late response
‑ Non contiguous data† (2 usec.)†††††††††††††††††††
‑ Word count error†††††††††††††††††††††††††††††††††††††††††
‑ Data on two channels†††††††††††††††††††††††††††††††††††††
- Status word
- Invalid Word
†††††††† M A X I M U M
R A T I N G S
†† +5 / +3.3 Volts +/‑ 5%
† +12 Volts +/‑ 5%
†1/2 Size PCI card
† 0 to† +70 Deg. C
‑65 to +150 Deg. C
0.24 Amps Max††††††
0.100 Amps 50% duty cycle†
†4.2 x 6.9 x 0.47 inches
†††† The PCI301 comes with software drivers for DOS and† Windows 98/NT/2000/XP. A set of well-documented APIís with Source code written in "C" is included.
†††† A menu driven user interface is included for stand-alone operation. With this program the user can set up 1553 traffic, simulate RT'S responses, monitor all or selected traffic in real time and capture data using trigger and search arguments.†
†††† The PCI301 data filter looks at the complete command rather than just addresses and sub addresses. The user designates individual Mes≠sages to be ignored, monitored, replied to or monitored and replied to.
†††† The PCI301 processes 1553 messages with a minimum attention from the CPU. The user need only write a set of command Blocks, a message list and number of messages to define a minor frame of 1553 messages. He writes a minor frame time, the number of minor frames per major frame and a minor frame list to define a major frame. The bus controller sends the major frame a number of times as programmed in the major frame count, without any further attention from the CPU.
†††† In the Remote Terminal mode, the user writes a set of command Blocks and a look-up table for the PCI301 to respond autonomously to incoming messages. In both modes an active monitor analyzes, annotates and stores bus traffic in a monitor Buffer.
†††† The PCI301 generates ten interrupt flags to show completion of a frame in the BC mode, receipt of a specified message, receipt of a specified Data word, receipt of a specified Status word, detected message errors or triggers.
- Direct coupling
- Transformer stub coupling
†††† The PIC301 operates as a 32 bits, target-only device with interrupt support. An auto indexing Dual ported, static RAM serves as the intermediate for data exchange between the on board PCI FIFO and the 1553 bus. An auto incrementing address register serves to hold the initial RAM Address and increments after each data transfer. Two additional registers control the mode of operation.
†††† Both the registers and the RAM can be loaded with new data while a message is being transmitted over the 1553 channel for real time applications. Essentially, programming the PCI301 consists of transferring data to or from the RAM and the host.
For specialized features or unique interface requirements, please contact the factory.
Specifications subject to change without notice.
Copyright (c) 2003 - 2007 by Andor Design Corp.
All rights reserved.
ANDOR DESIGN CORP. ††††††††††††††††††††††††††††††††† www.AndorDesign.com
20 Pond View Drive†††††††††††††††††††††††††††††††††††††††††††††††††††††††††† Telephone 516 364 1619
Syosset, New York, USA 11791-4409†††††††††††††††††††††††††††††††††††††††† FAX 516 364 5428
Data Sheet. Mar 1, 2007